1. Field of the Invention
The present invention relates to a device for detecting an error in a decoding result of an error correction code, for example, in a communications system or a broadcasting system, and a method thereof.
2. Description of the Related Art
In recent years, cellular phones have made remarkable progress and their market has rapidly been expanding. For such cellular phones, their communication devices must be reduced in size and consumption power, etc. A cellular phone of a smaller size, which is handy to carry, is considered to exploit a new market. Furthermore, if a cellular phone can support not only conventional voice communications but also data communications of, what is called, multimedia information such as documents, images, etc., its market value becomes very much large. Since such a cellular phone supporting data communications of multimedia information, etc. requires a large communication capacity as described above, it is vital to realize a large capacity communication with the smallest and simplest possible circuitry configuration. For this realization, it is inevitable to reduce an internal communication device in scale, weight, and size.
FIG. 1 is a block diagram showing the outline of the configuration of a conventional receiving device performing an error correction in reception data by using viterbi decoding which is one method of maximum likelihood decoding being one of error correction techniques in data communications, and CRC parity checking.
In this figure, remaining configuration except for the principal part relating to the present invention is omitted.
With viterbi decoding, data is decoded from its end. Therefore, also decoded data is output from its end to start. However, CRC checking cannot be made for viterbi-decoded data unchanged, which also affects data processing at subsequent stages. Therefore, after the bit order of viterbi-decoded data is inverted by storing the data output from a viterbi decoder 601 in a trace memory 603 and by reading the data from its start out of the trace memory 603, CRC parity checking and reception data process are performed. The decoded data read from the trace memory 603 is transmitted to a CRC parity checking unit 604, and also to a suitable processing circuit according to the type of the data. By way of example, after control data is converted from serial to parallel in a serial-to-parallel converter 605, the parallel data is written to a reception buffer 606. Upon completion of the write operation of the parallel data, a CPU 607 starts to read the data from the reception buffer 606, and performs the corresponding process.
The band of a signal received from an antenna not shown is converted from an RF band to a baseband via an IF band. Then, the signal is deinterleaved by a deinterleaver 600, and input to a viterbi decoder 601. The viterbi decoder 601 is composed of a viterbi decoding circuit 602 and the trace memory 603. As described above, the decoded data output from the viterbi decoding circuit 602 is output from its end to start in accordance with the decoding method. The trace memory 603 temporarily stores the data output from the viterbi decoding circuit 602, and outputs the decoded data from its start to end under the control of a controlling unit not shown.
The decoded data output from the viterbi decoder 601 is input to the CRC parity checking unit 604. The CRC parity checking unit 604 is a parity checking circuit which comprises a CRC circuit having the same configuration of that on a transmitting side. This unit generates a CRC bit for the decoded data with the CRC circuit, and determines whether or not the reception data includes an error by determining whether or not the generated CRC bit equals the CRC bit at the end of the decoded data. The determination result is notified from the CRC parity checking unit 604 to the CPU 607 or an adapter (ADP) 608 processing image data, etc.
The CPU 607 extracts the control data from the data stored in the reception buffer 606, and performs control according to the contents of the control data. The data decoded by the viterbi decoder 601 is input also to the adapter 608 or a voice codec 609. The adapter 608 or the voice codec 609 presents the input decoded data to a user as image or voice information via a facsimile 610, a PC 611, or a speaker 612.
FIG. 2 shows the format of normal transmission data before convolutional encoding for viterbi decoding is not performed.
A CRC bit 616 is appended to the end of data to be transmitted (original data) 615 on a transmitting side as shown in this figure, and CRC checking is made on a receiving side, so that an error in the reception data can be detected. If an error is detected in the reception data, a receiving terminal performs processes such as a process for requesting a transmitting station to retransmit the same data.
FIG. 3 is a block diagram showing the configuration of a CRC circuit 619 arranged on a transmitting side.
The CRC circuit 619 shown in this figure comprises flip-flops 620 (D1) through 622 (D3), a selector 625 for controlling output data, and exclusive-OR operation units EXORs 623 and 624.
Before the data 615 is input, all of the flip-flops 620 through 622 within the CRC (operation) circuit 619 are initialized (initiated to xe2x80x9c0xe2x80x9d). Then, the data 615 is input in bits, and a CRC operation is performed. The input data is captured into the CRC circuit 619 via the EXOR 624. The CRC operation is performed for the entire input data, so that a CRC parity bit is generated. However, since the selector 625 selects a terminal xe2x80x9caxe2x80x9d while the CRC operation is performed, output data becomes the same as the input data. The states of the flip-flops 620 through 622 when the data 615 is input to the end become the CRC parity bit 616. FIG. 3 shows the circuit for generating the CRC parity bit 616 composed of 3 bits. When the entire input data is output, the selector 625 selects a terminal xe2x80x9cbxe2x80x9d, and outputs the CRC parity bit 616 sequentially from D3 (flip-flop 622), D2 (flip-flop 621), to D1 (flip-flop 620). The output result 626 from the CRC circuit 616 is convolutional-encoded by a convolutional circuit which is not shown in this figure and arranged at the stage succeeding the CRC circuit, and is converted into a code which can be viterbi-decoded on a receiving side.
FIG. 4 shows the configuration of a CRC parity checking circuit 627 arranged in the device on a receiving side of the transmission data which is shown in FIG. 2 and is convolutional-encoded.
To make CRC parity checking on the receiving side, a CRC circuit 630 having the same configuration as that on a transmitting side is conventionally arranged. With this CRC circuit 630, the CRC parity bit of the data corresponding to the original data 615 of the decoded data 629 obtained with viterbi decoding is operated. The result of the CRC operation when the data corresponding to the original data 615 of the decoded data 629 is input to the CRC circuit 630 to its end is temporarily stored in a CRC operation result storing unit 632. Next, the CRC parity bit 616 appended on the transmitting side, that is, the CRC parity bit at the end of the decoded data 629 is extracted from the decoded data 629, an is stored in a storing unit 633. Then, the comparison between the bit value stored in the CRC operation result storing unit 632 and the bit value stored in the storing unit 633 is made. If they match, no error is determined to exist in the reception data. If they mismatch, an error is determined to exist in the reception data.
Conventionally, an error in reception data is detected by making CRC parity checking with the CRC circuit 630 having the same configuration as that of the CRC circuit 619 arranged in the device on a transmitting side as described above.
FIG. 5 explains the method for controlling a conventional reception buffer on a receiving side.
The bit string of the decoded data 629 decoded by the viterbi decoder 601 shown in FIG. 1 is serially input to the serial-to-parallel converter 605. After the bit string of the decoded data 629 is converted into parallel data in predetermined bits by the serial-to-parallel converter 605, it is input to the reception buffer 606. The parallel data is written to the reception buffer 606 sequentially from an address xe2x80x9c0xe2x80x9d. Then, the controlling unit not shown determines whether or not the write operation of the decoded data 629 is completed up to the last address (an address xe2x80x9cNxe2x80x9d equivalent to the length of one packet of the data) (636). If the write operation is determined not to be completed, the write address in the reception buffer 606 is incremented by 1 (637). The next data is then stored in the address obtained by incrementing the above described address in the reception buffer 606. If the write operation is determined to be completed up to the address xe2x80x9cNxe2x80x9d in the reception buffer 606, permission to read from the reception buffer 606 is notified to a CPU (638).
As described above, the viterbi decoder 601 decodes and outputs original data from its end to start. This is because the viterbi decoder 601 decodes the data retroactively from the end while making a maximum likelihood determination. However, since the CRC parity checking circuit 627 shown in FIG. 4 obtains a CRC parity bit with the CRC circuit 630 having the same configuration as that on a transmitting side, the decoded data to be fed to the CRC circuit 630 must be input sequentially from its start to end. Therefore, a trace memory 603 must be arranged to reverse the bit order of the data decoded by the viterbi decoder 601 before the decoded data is input to the CRC parity checking unit 604. Furthermore, accesses must be made to the trace memory 603, which causes a processing delay.
An object of the present invention is to provide an error detecting device with a small processing delay, which is reduced in circuitry scale and consumes less power, and a method thereof.
A device according to the present invention is an error detecting device for detecting an error in a decoding result with an input of the decoding result of the code obtained by encoding a message composed of data and the parity bit of the data, which is appended to the end of the data. This device comprises: an operating unit, to which a bit string of a decoding result is input in a decoding order, for performing an operation process for generating a parity bit for all of bits except for the decoded value of the parity bit within the bit string by recognizing as an initial value the decoded value of the parity bit within the bit string, and for performing an inverse operation process; and a determining unit for determining whether or not the decoding result is an error by detecting whether or not the final operation result matches the initial state of the operation process for generating the parity bit.
A method according to the present invention is an error detecting method for detecting an error in a decoding result with an inout of the decoding result of the code obtained by encoding a message composed of data and the parity bit of the data, which is appended to the end of the data, comprising the steps of: (a) inputting a bit string of a decoding result in a decoding order; (b) performing an operation process for generating a parity bit for all of bits except for the decoded value of the parity bit within the bit string by recognizing as an initial value the decoded value of the parity bit within the bit string, and performing an inverse operation process: and (c) determining whether or not the decoding result is an error by detecting whether or not the final operation result obtained with the operation in step (b) matches the initial state of the operation process for generating the parity bit.
According to the present invention, an error in decoded data can be detected. by inputting the bit string of the decoded data sequentially in a decoding order, when original data is decoded from its end to start with a decoding process. Consequently, a conventionally required trace memory can be omitted, thereby reducing an error detecting device in size and power, and speeding up its processing.